Intel Core 2 Extreme QX9650 - first look

Posted at: 3:49am 29th October 2007 by James Gorbold

Meet the world's first 45nm Penryn CPU ...

PENRYN UNVEILED

However, Intel hasn’t only scaled down the transistors in the QX9650 – it’s also tweaked the architecture. This new architecture is known as Penryn, and it will make its appearance not only in the QX9650, but also in a whole range of non-Extreme edition Core 2 and Xeon CPUs over the next few months. Penryn isn’t a whole new architecture, but it does offer a number of improvements over the Core architecture that it’s based on.

The first major area of improvement is the radix divider, the part of the CPU that calculates subtractive algorithms. In a Core-architecture Core 2 CPU, the divider is known as radix-4 and it can calculate two bits per iteration. The Penryn architecture introduces a new 68-bit CSA/CPA divider known as radix-16, which can calculate four bits per iteration. This means that program loops with lots of subtractive type algorithms, such as ray tracing, run twice as fast.

The Penryn architecture also introduces a new feature known as the Super Shuffle Engine, which improves the performance of SSE instructions without software having to be recompiled. Closely tied to the Super Shuffle Engine is the introduction of SSE4. This adds a further 47 instructions to the X86 instruction set, and they’re designed to perform tasks related to video encoding and photo editing that would have previously taken several separate instructions.

As with previous additions to the X86 instruction set, applications will not support SSE4 automatically, and as the current Intel compilers do not support SSE4, this means supporting applications will have to be hand-written in machine code. As a result, it will probably be quite a while before SSE4-compatible applications start to appear in decent numbers.

Penryn-architecture CPUs also have an improved cache architecture, which now allows misaligned store results to be forwarded to a load. This helps to reduce cache latency and means misaligned store commands can be carried out without having to wait for the whole cache to refresh. Not only that, but Penryn-architecture CPUs have more Level 2 cache than Core-architecture CPUs. Dual-core Penryn architecture CPUs will have 6MB of shared Level 2 cache, versus 4MB for a dual-core Core architecture CPU, while quad-core Penryn architecture CPUs will have 12MB of Level 2 cache, versus 8MB for a quad-core Core architecture CPU.


PERFORMANCE

To see just how much of a difference the Penryn architecture’s improvements and larger Level 2 cache make, we tested the QX9650 head to head against its predecessor, the Core 2 Extreme QX6850. Both CPUs have four cores clocked at 3GHz and a 1,333MHz FSB, but the QX6850 is manufactured using a 65nm process and has two lots of 4MB Level 2 cache, while the QX9650 has two lots of 6MB Level 2 cache. On paper, both CPUs have the same 130W TDP.

First of all, we ran both CPUs through the 2007 version of our Media Benchmarks. In these tests the QX9650 proved 6 per cent faster than the QX6850. We also ran the standard Supreme Commander benchmark on both CPUs, but did not see any difference in the minimum or average frame rate.